News:
General Information:
Lecturer: Reza
Sarvari (office EE206)
Classes :
ZOJ 3:00-4:30 ;
Bargh 3
References: H.
B. Bakoglu; Circuits, Interconnections,
and Packaging for VLSI Interconnect
Technology
and Design for GSI Interconnect-Centric
Design for Advanced SOC and
NOC Interconnect
Analysis and Synthesis High-Speed
Digital System Design
Johnson, Graham; High
Speed Signal Propagation Syllabus:
see
Grades:
tentative
Homeworks/Exams
and solutions:
the only way to hand in solutions is
coursewrae homework01 [ITRS(IRDS update) reports
Link01 ]
homework02
homework03 (Ref[
1 ] Ref[
2 ])
homework04
homework05
Lectures: (
)
(
) History
(
) Introduction
(
) Introduction
+
b Introduction
(
) Introduction
(
) Introduction
(
) Maxwell’s Equations
(
) TEM Transmission Lines
(
) Resistance
(
) Capacitance
(
) Loop Inductance
(
) Partial Inductance
(
) solution of general TL
(
) Time domain solution of ideal TL
(
) RC regime: Elmore Delay, Sakurai
(
) RC regime: Xtalk, Noise, Ramp Input
(
) Distributed RLC, Davis Model
(
) Buffer Insertion RC regime
(
) Buffer Insertion RLC regime
(
) Wire-Length Distribution
older hws:
( Ref[
1 ] Ref[
2 ])
OLDER VCLASS:
Links to files + links to Google Drive Folders
Lectures: (
)
Solution to HWs:
EC
01
Slides/Handouts:
WinTLS
(Note: exe file, Save then Run!)
Click here
for my password protected page!
Paper
Pool: (in chronological order)
"The Transient Response of
Damped Linear Networks with Particular Regard to Wideband
Amplifiers, " Journal of Applied Physics, vol. 19, no. 1,
pp. 55-63, January 1948.
“Inductance Calculation in a
Complex Integrated Circuit Environment,” IBM
J. Res. Develop., Vol.16, pp.470-481, Sept. 1972. Simple Formulas for Two- and
Three-Dimensional Capacitances," IEEE Trans. Electron
Devices ED-30 pp. 183-185, Feb. 1983. "Optimal interconnection
circuits for VLSI," IEEE Trans. Electron. Devices Vol. 32,
No. 5, pp. 903–909, 1985. "Transmission line models for
lossy waveguide interconnections in VLSI," IEEE Trans.
Electron Dev., pp. 1356-1365, 1986. “Closed-form expressions for
interconnection delay, coupling and crosstalk in VLSI's,”
IEEE Trans. Electron Devices, vol.40, no.1, pp.118–124, 1993. “Interconnect scaling-the real
limiter to high performance ULSI,” IEDM, 1995. “Efficient Coupled Noise
Estimation for On-chip Interconnects,” IEEE Proc. ICCAD,
pp. 147-153. Nov. 1997. "Limit to the bit-rate capacity
of electrical interconnects from the aspect ratio of the system
architecture," Journal of Parallel and Distributed
Computing, Vol. 41, No. 1, Jan 1997, pp.42-52. "Limit to the bit-rate capacity
of electrical interconnects from the aspect ratio of the system
architecture," IEEE Trans. on CAD , Vol. 17, No. 8, Aug 1998,
pp.645-654. "A stochastic wire-length
distribution for GigaScale Integration (GSI)—Part I: Derivation and
validation," IEEE Trans. on Electron Devices.1998,
45(3):580-589 "Crosstalk
in VLSI Interconnections," IEEE Trans on Computer-Aided
Design of Integrated Circuits and Systems, vol. 18, no. 12, pp.
1817-1824, December 1999. "Compact distributed rlc
interconnect models - Part I: Single line transient, time delay and
overshoot expressions," IEEE Transactions on Electron
Devices, Vol. 47, No.11, pp. 2068–2077, November 2000."Compact
Distributed RLC Interconnect Models—Part II: Coupled Line Transient
Expressions and Peak Crosstalk in Multilevel Networks”,"
IEEE Transactions on Electron Devices, Vol. 47, No.11, pp. 2078-2087,
November 2000."Interconnect Limits on
Gigascale Integration. (GSI) in the 21st Century,"
Proceedings of the IEEE, Vol 89, No. 3, March 2001.“Time Domain Modeling of Lossy
Interconnects” , IEEE Trans. Advanced. Packaging, Vol. 24,
No. 2, May 2001."Analysis of On-Chip Inductance
Effects for Distributed RLC Interconnects," IEEE
Transactions on Computer-Aided Design of Integrated Circuits and
Systems, Vol 21, No. 8, August 2002.
Lectures: Review of VLSI technology
o Moore’s
Law (
) (
)
o Trends
and challenges in scaling
o
Evolution of Interconnects
o Future
of Interconnects
Scaling Issues (
o Device
and Interconnect limitations
o
Material and circuit solutions
o
Electromigration (voids / hillocks)
Interconnect Fabrication (
o Wet
substrate etching
o
Lift-off technique
o
Reactive ion etching
o Dual
damascene (copper)
o Limits
on wire width (erosion and dishing)
Wire length distribution
o Rent's rule (
)
o Davis
model (
) (
)
Transmission Line Review + Definitions
o Plane
wave equations
o TEM
Mode for lossless and lossy metal wires
o
Inductance (partial inductance, loop inductance)
o
Capacitance (decoupling capacitance)
o
Resistance (size effects, surface roughness, grain scattering, liners)
Interconnects
as Transmission Line
o Skin
effect
o Delay
calculations, RC vs RLC line (Elmore delay,Sakurai delay)
o Ramp
input
o Noise
(victim/source ,noise vs. signal rise time) in/out of phase switching (
)
o Multi
level interconnect network
o
Repeater insertion (optimal repeater)
o Power
dissipation (dynamic power, leakage power, short circuit power)
o Power
optimization (Lagrangian Multiplier)
o Power
distribution network
o Clock
networks
o
Bit-rate limitations
o IntSim
CAD Tool!
Novel Solutions
o Optical
Interconnect
o Carbon
Nanotubes/Graphene vs. Copper wires
Same/Ralated
Courses at
Other Schools!
Research Groups:
Useful Links:
Google Drive
Lecture
00
Lecture
01
COMSOL training